Implementation method for 3D integrated circuit |
Title： |
| Implementation method for 3D integrated circuit |
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Application Number： |
200710118827 |
Application Date： |
2007/06/12 |
Announcement Date： |
2007/11/28 |
Pub. Date： |
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Publication Number： |
101079386 |
Announcement Number： |
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Grant Date： |
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Granted Pub. Date： |
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ApplicationType： |
Invention |
State/Country： |
11[] |
IPC： |
H01L 21/60 |
Applicant(s)： |
Tsinghua University |
Inventor(s)： |
Wang Zheyao, Song Chongshen, Cai Jian, Liu Litian |
Key Words： |
3D, integrated circuit, Implementation |
Abstract： |
The invention discloses a realizng method of three-dimensional integrated circuit in the semiconductor making technique and three-dimensional integrated technical domain, which comprises the following steps: sedimenting plating seed layer on the bonding face of the first circuit disc or auxiliary disc; making the auxiliary disc as the through-hole to reduce the back to support the first layer of circuit disc and etch the disc; exposing the plating seed layer through the through-hole; using plating technique from bottom to top; adopting the plating seed layer as original; plating to fill the through-hole; making projection on the filled through-hole; adopting bonding pattern to connect the first layer of circuit disc and the second layer of circuit disc. The invention reduces the technical difficulty to realize three-dimensional integration on the silicon substrate, which has good versatility. |
Claim： |
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Priority： |
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PCT： |
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LegalStatus： |
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