Method for reducing analog-digital converter capacitance mismatch error based on capacitance match |
Title: |
Method for reducing analog-digital converter capacitance mismatch error based on capacitance match |
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Application Number: |
200610089397 |
Application Date: |
2006/06/23 |
Announcement Date: |
2006/11/22 |
Pub. Date: |
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Publication Number: |
1866749 |
Announcement Number: |
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Grant Date: |
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Granted Pub. Date: |
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ApplicationType: |
Invention |
State/Country: |
11[China|beijing] |
IPC: |
H03M 1/12, H03M 1/10 |
Applicant(s): |
Tsinghua University |
Inventor(s): |
Li Fule, Wang Zhihua |
Key Words: |
reducing, analog-digital converter, capacitance mismatch error, capacitance match |
Abstract: |
The invention discloses a reducing analogue digital converter capacitance dismatch error method in the integrated circuit design technique domain, which is characterized by the following: four work capacitances of analogue-digital converter are defined the two capacitances which two roofs connects to input amplifier positive carry-in terminal are C1and C2 the capacitances which two roofs connects to input amplifier negative carry-in terminal are C3 and C4 C1 and C3 are the first pair of difference displacement volume C2 and C4 are the second pair of difference displacement volume the two pairs of difference displacement volumes are the difference sampling capacitance or difference feedback capacitance of grade circuit comparing four work capacitances forms two pairs of new difference work capacitances one pair of difference work capacitance with the smaller capacitance value is used for grade circuit difference feedback capacitance. The invention doesn''t improve the circuit power consumption and doesn''t reduce the load speed. |
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Priority: |
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PCT: |
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