Over-all wiring method for standard units based on optimized time delay and key network techniques
Title：
Over-all wiring method for standard units based on optimized time delay and key network techniques
Application Number：
 02100354
Application Date：
 2002/01/15
Announcement Date：
 2002/07/24
Pub. Date：
Publication Number：
 1360268
Announcement Number：
 1150481
Grant Date：
 2004-5-19
Granted Pub. Date：
 2004-5-19
ApplicationType：
 Invention
State/Country：
 11[China|beijing]
IPC：
 G06F 17/50
Applicant(s)：
 Qinghua Univ
Inventor(s)：
 Hong Xianlong, Jing Tong, Bao Haiyun
Key Words：
 Over-all wiring method, standard units, optimized time delay, key network techniques
Abstract：
 An over-all wiring method for standard units with optimized time delay includes creating over-all wiring diagram, configuring initial wiring tree with the shortest length, configuring key network composed of key pins, key sides and the weight, virtual source point and convergent point of each orientative side, reconfiguring the wiring tree from a group of sides with minimal division for reducing time delay, comparing the given delay data with optimized delay, and iterating to obtain wiring tree of over-all network.
Claim：
Priority：
PCT：
LegalStatus：

Recommend this patent:
1 2 3 4 5
Average ( 0 votes):
                                                                          Recommended Patents>>

Relevancy information



Other Patents of Same Inventor

Integrated circuit macro-module layout design based on module deformation and placement method
Integrated wiring method of standard units with carrying optimization of time delay based on considering coupling effect
Steiner tree method for O (nlogn) under 4-geometry
Right angle wiring tree method for wire length optimized obstacle passing
Analog circuit layout oriented symmetrical constraint extraction method based on graph isomorphism
Integrated circuit layout plan and buffer plan integrated layout method
Method for improving loading efficiency of container based on minimum freedom degree poriority principle
Rectangular steiner tree method of super large size integrated circuit avoiding barrier
Integrated circuit power supply network transient analytical solving method based on multi-layer equivalent circuit model
Large-scale hybrid mode layout method based on virtual module
Time delay driving method of right angle Steiner tree under obstruction when making loose routing for standard units
High speed high precision transient simulation method able to process tree net hybrid power supply structure in VLSI
Generally distributing method of standant unit for eliminating crosstalk caused by coupling inductance
Integrated circuit module level distributing method based on module deformation and probability local search
Crosstalk eliminating loose routing method based on power/ground grid and row alignment
Transient state analyzing method for hierarchy power supply / earth cord network based on loose operations
Standard unit overall wiring method of multi-terminal network plug-in buffer optimizing delay
Automatic wiring method of analog integrated circuit based on multiple step length labyrinth algorithm
Fast method for analyzing IC wiring possibility



News & Events More>>

Last Update  
2008-4-17
  Selected patents owned by Tsinghua University filed in 2005 are loaded.
2008-3-31
  Selected patents owned by Tsinghua University filed in 2006 and 2007 are load.







Copyright 2008-2015 All Rights Reserved Patent License of China.      Designed by Easygo