Montgomery analog multiplication algorithm for VLSI and VLSI structure of intelligenjt card analog multiplier
Title：
Montgomery analog multiplication algorithm for VLSI and VLSI structure of intelligenjt card analog multiplier
Application Number：
 02125399
Application Date：
 2002/07/31
Announcement Date：
 2003/01/22
Pub. Date：
Publication Number：
 1392472
Announcement Number：
 1230736
Grant Date：
 2005-12-7
Granted Pub. Date：
 2005-12-7
ApplicationType：
 Invention
State/Country：
 11[China|beijing]
IPC：
 G06F 7/552, H04L 9/28
Applicant(s)：
 Tsinghua Univ.
Inventor(s)：
 Li Shuguo, Zhou Runde, Sun Yihe
Key Words：
 Montgomery analog multiplication algorithm, VLSI structure, intelligenjt card analog multiplier
Abstract：
 The present invention relates to the encryption and decryption technology and features that it is one algorithm with high degree of parallelism and suitable for VLSI implementation. The thrice large number multiplications of primary montgomery analog multiplication are decomposed into 2ss+s times small number multiplications. The VLSI structur for the intelligent card analog multiplifier is one high-order analog multiplier, which has 32 bit multiplier to complete 1024 bit analog multiplication and three stage parallel flow water structure in the data passage. Compared with available structure, the present invention has reduced chip area and analog multiplication clock number and can realize digital signature and confirmation of RSM algorithm in intelligent card.
Claim：
Priority：
PCT：
LegalStatus：

Recommend this patent:
1 2 3 4 5
Average ( 0 votes):
                                                                          Recommended Patents>>

Relevancy information



Other Patents of Same Inventor

2D scan tree structure for measurable scan design of low-power integrated circuits
Large number multiplier based on secondary Booth coding
Carry generating circuit for CMOS power-consumption balance delay-sensitive less adder
AES encrypted circuit structure for data stream executed in desequencing
Low power consumption and low clock swing range D trigger based on C2MOS and sensitive amplifier structure
Low power consumption clock swing range D trigger
Low-voltage and low-power dissipation pseudo-two stage Class-AB OTA structure
Register file of elliptic curve cipher
Transient current measuring method and system for IC chip
Full complementary MOS exhaustion region condenser network aimed at low voltage application
Code decode apparatus for video standard application
Filtering method and system of deblocking effect filter



News & Events More>>

Last Update  
2008-4-17
  Selected patents owned by Tsinghua University filed in 2005 are loaded.
2008-3-31
  Selected patents owned by Tsinghua University filed in 2006 and 2007 are load.







Copyright 2008-2015 All Rights Reserved Patent License of China.      Designed by Easygo