System for improving SRAM process EPGA design safety by asynchronous circuit
Title：
System for improving SRAM process EPGA design safety by asynchronous circuit
Application Number：
 200610011704
Application Date：
 2006/03/31
Announcement Date：
 2006/11/08
Pub. Date：
Publication Number：
 1858722
Announcement Number：
Grant Date：
Granted Pub. Date：
ApplicationType：
 Invention
State/Country：
 11[China|beijing]
IPC：
 G06F 12/14, G06F 21/00, G06F 17/50
Applicant(s)：
 Tsinghua Univ.
Inventor(s)：
 Zeng Lieguang, Jin Depeng, Chen Wentao, Kong Lingkai
Key Words：
 improving, SRAM process, EPGA design, safety, asynchronous circuit
Abstract：
 This invention relates to the security of the FPGA of the SRAM technology characterizing in adding an asynchronous sampling step in the FPGA circuit to let a cryptographic key selection state set select the FPGA cryptographic key from an internal list of the FPGA randomly, at the same time, the cryptographic key transfer instruction sent to CPLD is a random sequence, besides, M sequence de-cipher and cipher circuit are added in the FPGA and CPLD, so the cryptographic keys from CPLD to FPGA should be ciphered by the M sequence to increase the anti-attack ability of the system and the transfer of cryptographic state increases difficulty in recognization and interpretation since a cribber should master numbers of state machines and their ruleless transfer modes.
Claim：
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PCT：
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