Integrated wiring method of standard units with carrying optimization of time delay based on considering coupling effect
Title：
Integrated wiring method of standard units with carrying optimization of time delay based on considering coupling effect
Application Number：
 02156622
Application Date：
 2002/12/17
Announcement Date：
 2003/05/07
Pub. Date：
 2006/10/11
Publication Number：
 1416082
Announcement Number：
 1279480
Grant Date：
 2006-10-11
Granted Pub. Date：
 2006-10-11
ApplicationType：
 Invention
State/Country：
 11[China|beijing]
IPC：
 G06F 17/50
Applicant(s)：
 Tsinghua Univ
Inventor(s)：
 Hong Xianlong, Jing Tong, Xu Jiangyu
Key Words：
 Integrated wiring method, standard units, optimization time delay, coupling effect
Abstract：
 Standard unit general routing method of coupling effect in time delay optimization characterizes in making up time delay optimization routing tree under the condition that any of the wire nets is not restrained to further optimize outing congestion to estimated the link electricity parameter with successively connected linking load model based on empiric analog after elimianting congestion edge, to compute the link delay with congruence variation technology to compute gate delay etc. three steps to calculate the path general delay value with looking-up table+interpolation based on the delay information table given by user, then enhancing to considerate the key path up wire net weighted value of the couple effect to reduce routing density adjacent to the wire net, so as to reduce couple condenser and general path delay to optimize the circuit time delay.
Claim：
Priority：
PCT：
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