Hierarchy programmable parallel video signal processor structure for motion estimation algorithm |
Title: |
Hierarchy programmable parallel video signal processor structure for motion estimation algorithm |
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Application Number: |
00130074 |
Application Date: |
2000/10/27 |
Announcement Date: |
2001/03/28 |
Pub. Date: |
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Publication Number: |
1289212 |
Announcement Number: |
1127264 |
Grant Date: |
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Granted Pub. Date: |
2003-11-5 |
ApplicationType: |
Invention |
State/Country: |
11[China|beijing] |
IPC: |
G06F 17/00, G06T 9/40, H04N 7/24 |
Applicant(s): |
Qinghua Univ. |
Inventor(s): |
He Yun, Gong Danian |
Key Words: |
Hierarchy programmable, parallel, video signal processor structure, motion estimation algorithm |
Abstract: |
The present invention relates to the field of video-frequency image coding technology, including six portions of low-layer instruction unit, parallel arithmetic unit, data routing unit, memory and address formation unit, high-layer instruction unit and external memory interface unit, in which the low-layer instruction unit is respectively connected with high-layer instruction unit and parallel arithmetic unit via control signal wire, and the data routing unit is respectively connected with parallel arithmetic unit and memory and address formation unit via data bus. Said invention can simultaneously implement multi-block matching algorithm on one structure, can reduce hardware expense in video-frequency coding system and can support other algorism of video-frequency coding. |
Claim: |
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Priority: |
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PCT: |
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