2D scan tree structure for measurable scan design of low-power integrated circuits
Title：
2D scan tree structure for measurable scan design of low-power integrated circuits
Application Number：
 00135864
Application Date：
 2000/12/22
Announcement Date：
 2001/07/25
Pub. Date：
 2003/10/08
Publication Number：
 1305112
Announcement Number：
 1123781
Grant Date：
Granted Pub. Date：
 2003-10-8
ApplicationType：
 Invention
State/Country：
 11[China|beijing]
IPC：
 G01R 31/28, H01L 27/02
Applicant(s)：
 Qinghua Univ
Inventor(s)：
 Sun Yihe, Xu Lei, Chen Hongyi
Key Words：
 2D, scan tree structure, measurable scan design, low-power integrated circuits
Abstract：
 A 2D scan tree structure for the measurable scan design of low-power IC includes scanning N registers. It features that a 2D array (LXH) composed of H groups of scan chain circuits and L groups of serial scan chain circuits is used to constitute a scan tree, where LXH=N. Its advantages are simple interconnection between registers, ability to constitute local scan chain as required, and low requirement to optimize timer tree.
Claim：
Priority：
PCT：
LegalStatus：

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