CPU restraint forming and verifying method based on boundary condition and self detection random test
Title：
CPU restraint forming and verifying method based on boundary condition and self detection random test
Application Number：
 200410101821
Application Date：
 2004/12/24
Announcement Date：
 2005/10/19
Pub. Date：
 2007/09/05
Publication Number：
 1684047
Announcement Number：
 100336032
Grant Date：
 2007-9-5
Granted Pub. Date：
 2007-9-5
ApplicationType：
 Invention
State/Country：
 11[China|beijing]
IPC：
 G06F 11/36
Applicant(s)：
 Tsinghua Univ.
Inventor(s)：
 Yao Wenbin, Zhang Youhui, Wang Jinglei
Key Words：
 CPU, restraint forming, verifying method, boundary condition, self detection, random test
Abstract：
 The present invention belongs to the field of automatic computer verifying technology, and is the CPU restraint creating and verifying method based on boundary condition and random self test. The specific mode is one random test environment including system structure model and RTL model. The system structure model is expected processor model realized with C simulator and used as the standard reference model. The RTL model is one to be tested and verified, and the random test and verification aims at testing the consistency of the RTL model to the system structure model. Both the RTL model and the system structure model can output separate processor state in each clock period, and comparing the processor state of these two model can judge the consistency. The present invention has independent system structure, and can constitute new verifying platform easily to raise the verification speed and quality greatly.
Claim：
Priority：
PCT：
LegalStatus：

Recommend this patent:
1 2 3 4 5
Average ( 0 votes):
                                                                          Recommended Patents>>

Relevancy information



Other Patents of Same Inventor

Memory-network memory-magnetic disc high speed reliable storage system and its reading/writing method
Fast synchronous and high performance journal device and synchronous writing operation method
Structure-irrelevant micro-processor verification and evaluation method
Method for improving compute system disc synchronous writing property based on movable memory
Single-chip analog system with multi-processor structure



News & Events More>>

Last Update  
2008-4-17
  Selected patents owned by Tsinghua University filed in 2005 are loaded.
2008-3-31
  Selected patents owned by Tsinghua University filed in 2006 and 2007 are load.







Copyright 2008-2015 All Rights Reserved Patent License of China.      Designed by Easygo