Design method for sequential logic digital circuit
Title：
Design method for sequential logic digital circuit
Application Number：
 200310121721
Application Date：
 2003/12/19
Announcement Date：
 2004/12/08
Pub. Date：
Publication Number：
 1553577
Announcement Number：
Grant Date：
Granted Pub. Date：
ApplicationType：
 Invention
State/Country：
 11[China|beijing]
IPC：
 G06F 7/00H03K 19/00
Applicant(s)：
 Tsinghua Univ.
Inventor(s)：
 Zeng Lieguang, Jin Depeng, Liu Zhao
Key Words：
 Design method, sequential logic, digital circuit
Abstract：
 This invention is relative to a design method for time sequence logical digit circuit, it belongs to the digit circuit design technology field. The method first sets S kinds of states in the time sequence digit circuit and inputs M kind of conditions into the time sequence digit circuit. There are P kinds of actions in the time sequence logic digit circuit. Builds up the index table describing the translating between any two states within the S status. Builds up the index table among the status, actions and conditions. The advantages of this invention are to covert the series state machine in existing digital circuit system into parallel state machine, adapt it to the parallel technology in the digital circuit system.
Claim：
Priority：
PCT：
LegalStatus：
 2007-2-7Date of deemed withdrawal

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