High-speed master-slave type D trigger in low power consumption |
Title: |
High-speed master-slave type D trigger in low power consumption |
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Application Number: |
200510086788 |
Application Date: |
2005/11/04 |
Announcement Date: |
2006/04/19 |
Pub. Date: |
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Publication Number: |
1761153 |
Announcement Number: |
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Grant Date: |
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Granted Pub. Date: |
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ApplicationType: |
Invention |
State/Country: |
11[China|beijing] |
IPC: |
H03K 3/012, H03K 3/26 |
Applicant(s): |
Tsinghua Univ. |
Inventor(s): |
Yang Huazhong, Gao Hongli, Qiao Fei, Wang Hui |
Key Words: |
High-speed, master-slave type, D trigger, low power consumption |
Abstract: |
D trigger is composed of driving and triggering two parts of cascaded circuits. The driving circuit includes transmission gate, timeclock controlled inverting circuit and an inverter. Triggering circuit is a difference structure controlled by the timeclock controlled inverting circuits. On/off of transmission gate is controlled by timeclock singnal; when signal is in high, transmission gate is off; and when signal is in low, transmission gate is on. In on state of the transmission gate, input signal in high level is sent to trigger; when next timeclock signal in high level comes, transmission gate is turned to off; and timeclock controlled inverting circuit is turned to on to hold electrical level, and meanwhile trigger is flipped. Advantages are: simple circuit structure, few number of transistor, small area, about 40£¥ less than power consumption of traditional trigger, and about 20£¥ less than delay time. Moreover, difference input in second stage enhances performance for antinoise. |
Claim: |
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Priority: |
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PCT: |
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