High-performance low-clock signal excursion master-slave D type flip-flop |
Title: |
High-performance low-clock signal excursion master-slave D type flip-flop |
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Application Number: |
200510086436 |
Application Date: |
2005/09/16 |
Announcement Date: |
2006/03/01 |
Pub. Date: |
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Publication Number: |
1741381 |
Announcement Number: |
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Grant Date: |
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Granted Pub. Date: |
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ApplicationType: |
Invention |
State/Country: |
11[China|beijing] |
IPC: |
H03K 3/012, H03K 3/037, H03K 3/356 |
Applicant(s): |
Tsinghua Univ. |
Inventor(s): |
Yang Huazhong, Gao Hongli, Qiao Feng, Wang Hui |
Key Words: |
High-performance, low-clock signal, excursion, master-slave, D type flip-flop |
Abstract: |
A master ¨C slave type of D trigger with low maximum deflection clock signal consists of phase inverter for reversing low maximum deflection clock signal , PMOS tube grid and drain electrode being connected to each other to form active load for lowering supply voltage of phase inverter , trigger driving circuit including clock signal input and trigger signal input , slave triggering circuit with its driving signal input end being connected to trigger driving circuit and its clock signal input end being connected to phase inverter . It features that slave triggering circuit is turned over to let correct signal to be inputted when clock signal leading edge is arrived . |
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