Synchronous enabled type condition presetting CMOS trigger |
Title: |
Synchronous enabled type condition presetting CMOS trigger |
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Application Number: |
200510011905 |
Application Date: |
2005/06/09 |
Announcement Date: |
2005/11/30 |
Pub. Date: |
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Publication Number: |
1702963 |
Announcement Number: |
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Grant Date: |
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Granted Pub. Date: |
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ApplicationType: |
Invention |
State/Country: |
11[China|beijing] |
IPC: |
H03K 3/012, H03K 3/037, H03K 3/356 |
Applicant(s): |
Tsinghua University |
Inventor(s): |
Qiao Fei, Wang Haibing, Wang Hui, Yang Huazhong |
Key Words: |
Synchronous enabled type, condition presetting, CMOS trigger |
Abstract: |
This invention relates to simultaneous CMOS trigger in D trigger technique field, which is characterized by the following: it is composed of simultaneous circuit and first and second locking connection, wherein, the circuit comprises two CMOS transmission gates for inputting data signal and one output signal of the second locker and the two gates outputs the data signals to the first locker under the control of the anti-phase signals. The first locker adopts input data controlled pre-charging circuit and the second locker adopts two same circuits parameter single phase clock, wherein, the output end is symmetric to the down end with one circuit of output end of the two locker to realize the stability of the clock signal in low level. |
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