Sensitive amplifier structured falling edge CMOS trigger |
Title: |
Sensitive amplifier structured falling edge CMOS trigger |
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Application Number: |
200510011937 |
Application Date: |
2005/06/15 |
Announcement Date: |
2005/11/16 |
Pub. Date: |
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Publication Number: |
1697320 |
Announcement Number: |
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Grant Date: |
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Granted Pub. Date: |
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ApplicationType: |
Invention |
State/Country: |
11[China|beijing] |
IPC: |
H03K 3/012, H03K 3/356 |
Applicant(s): |
Tsinghua Univ. |
Inventor(s): |
Qiao Fei, Wang Hui, Wei Dingli, Yang Huazhong |
Key Words: |
Sensitive amplifier structured, falling edge, CMOS trigger |
Abstract: |
Sensitive amplifier composed of two inverters connected to each other end to end constitutes first stage of the trigger. Two connected points form SALATCH_P and SALATCH_N nodes respectively. Two buffered inverters, two CMOS transfer gate, potential hold circuit, and output inverter connected to each other constitutes second stage. The said SALATCH_P and SALATCH_N are connected to input ends of the said buffered inverters respectively. The invention features simple structure, small area of circuit, low power consumption, and good characteristics of circuit time delay, setup time and metastable state time. |
Claim: |
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Priority: |
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PCT: |
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