High-speed low clock signal oscillation amplitude driving conditional precharging CMOS trigger
Title：
High-speed low clock signal oscillation amplitude driving conditional precharging CMOS trigger
Application Number：
 200510011539
Application Date：
 2005/04/08
Announcement Date：
 2005/09/14
Pub. Date：
 2007/11/07
Publication Number：
 1667950
Announcement Number：
 100347957
Grant Date：
 2007-11-7
Granted Pub. Date：
 2007-11-7
ApplicationType：
 Invention
State/Country：
 11[China|beijing]
IPC：
 H03K 3/356, H03K 3/012
Applicant(s)：
 Tsinghua University
Inventor(s)：
 Yang Huazhong, Qiao Fei, Wang Hui
Key Words：
 High-speed, low clock, signal oscillation, conditional precharging, CMOS trigger
Abstract：
 A high and low clock signal amplitude pre-fill CMOS trigger characterizes in connecting substrates of all PMOS tubes in the first stage latch of SAFF-CD conditional pre-fill structure driven by the low voltage amplitude clock signals to the power supply directly, the same time when omitting the only grating connected with NMOS tubes of the same supply end, two coupled NMOS tubes at the drain are removed, so that the drain of NMOS tubes with the substrate and the source all connected with the earth is connected with the drain of two remained NMOS tubes, finally, two compensated output ends of the first state latch are connected with two mutual independent single clock phase latches with the same circuit parameters.
Claim：
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PCT：
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