Bias compensation circuit for adjusting transconductance variation range of transistor in load
Title：
Bias compensation circuit for adjusting transconductance variation range of transistor in load
Application Number：
 200510011357
Application Date：
 2005/02/25
Announcement Date：
 2005/08/17
Pub. Date：
Publication Number：
 1655086
Announcement Number：
Grant Date：
Granted Pub. Date：
ApplicationType：
 Invention
State/Country：
 11[China|beijing]
IPC：
 G05F 3/24, G05F 3/26, H03B 5/08
Applicant(s)：
 Tsinghua University
Inventor(s)：
 Mao Xiaojian, Yang Huazhong, Wang Hui
Key Words：
 adjusting, load, transistor, transconductance variation range, bias compensation circuit
Abstract：
 A current mirror regulating trans-conductance variable sphere in load characterizes that its bias current source output end is parallel to a NMOS transistor to the earth, the grid of the transistor is connected with the central point of a resistor bleeder branch to make up of a bias compensation circuit, which can reduce the trans-conductance variance by 41.4% compared to NMOS transistors without said compensation in a LC oscillator.
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2008-4-17
  Selected patents owned by Tsinghua University filed in 2005 are loaded.
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