Low clock signal oscillation range condition prefilling CMOS trigger |
Title: |
Low clock signal oscillation range condition prefilling CMOS trigger |
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Application Number: |
200510058997 |
Application Date: |
2005/03/29 |
Announcement Date: |
2005/08/10 |
Pub. Date: |
2007/11/07 |
Publication Number: |
1652463 |
Announcement Number: |
100347956 |
Grant Date: |
2007-11-7 |
Granted Pub. Date: |
2007-11-7 |
ApplicationType: |
Invention |
State/Country: |
11[China|beijing] |
IPC: |
H03K 3/012, H03K 3/00 |
Applicant(s): |
Tsinghua Univ. |
Inventor(s): |
Yang Huazhong, Qiao Fei, Wang Hui |
Key Words: |
Low clock signal, oscillation range, condition prefilling, CMOS trigger |
Abstract: |
Following features forms characters of the CMOS trigger: substrates of all PMOS tube in first stage latch unit of trigger circuit driven by clock signal with low amplitude of oscillation possessing well known SAFF_CP conditional preliminary filling structure are connected to end of power source directly; a unique grid pole in first stage latch unit, which was connected to grid pole of NMOS tube in same end of power source before, is connected to signal end of time clock; complemental output ends of first stage latch unit are connected to two independent single phase time clock latch units with same circuit parameters respectively. The invention guarantees that complemental output ends of trigger realize symmetrical time delay of rising edge and time delay of falling edge. Comparing with SAFF_CP trigger circuit, the invention possesses advantages of small settling time, simple structure, and in favor of use and design for circuit. |
Claim: |
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Priority: |
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PCT: |
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