Method for realizing high-parallel frame predicator
Title：
Method for realizing high-parallel frame predicator
Application Number：
 200610113868
Application Date：
 2006/10/20
Announcement Date：
 2007/03/28
Pub. Date：
Publication Number：
 1937774
Announcement Number：
Grant Date：
Granted Pub. Date：
ApplicationType：
 Invention
State/Country：
 11[China|beijing]
IPC：
 H04N 7/32, H04N 7/26
Applicant(s)：
 Tsinghua Univ.
Inventor(s)：
Key Words：
 high-parallel, frame predicator, realizing method
Abstract：
 The invention belongs to Video decoder IC design field. The character is in that: to the same operation among the prediction formulas in 17 different prediction modes of 4x4 block with 16 pixels adopting digit computation strength cut method to remove computation redundance; providing a in-frame predictor system with high degree of parallelism, which can process the predicted values of 16 pixels within every clock cycle. From the results achieved, compared to the design with the use of reconstruction, this invention can decrease circuit area under same parallelism and simplifies the control logic.
Claim：
Priority：
PCT：
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