Carry generating circuit for CMOS power-consumption balance delay-sensitive less adder
Title：
Carry generating circuit for CMOS power-consumption balance delay-sensitive less adder
Application Number：
 200410101820
Application Date：
 2004/12/24
Announcement Date：
 2005/07/20
Pub. Date：
Publication Number：
 1641649
Announcement Number：
Grant Date：
Granted Pub. Date：
ApplicationType：
 Invention
State/Country：
 11[China|beijing]
IPC：
 G06F 17/50, H04L 9/30
Applicant(s)：
 Tsinghua Univ.
Inventor(s)：
 Sun Yihe, Li Xiangyu
Key Words：
 Carry generating circuit, CMOS, power-consumption balance, delay-sensitive less, adder
Abstract：
 The invention relates to a carry generating circuit that is used in CMOS power consumption balance delay non-sensitive leading carry summer. Its feature is that: a couple of crossed connecting PMOS tubes is contained in, and the drain electrode is the output end; a couple of PMOS tubes controlled by clock signal are used as charging switch; a couple of NMOS tubes are used as discharging switch; a evaluation network is set between charging switch and ground that contains a dynamic difference evaluation circuit constructed by carry removing, carry delivering, carry generating, input signal controlling tube and the corresponding balance tube, reset tube, to ensure a balance charge/discharge circuit would be available. The SNR of the power signal is increased nine times by using the invention.
Claim：
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PCT：
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2008-4-17
  Selected patents owned by Tsinghua University filed in 2005 are loaded.
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