A method for reducing circuit power consumption in large scale integrated circuit
Title:
A method for reducing circuit power consumption in large scale integrated circuit
Application Number:
200410038009
Application Date:
2004/05/14
Announcement Date:
2005/01/26
Pub. Date:
2007/05/02
Publication Number:
1571279
Announcement Number:
1314204
Grant Date:
2007-5-2
Granted Pub. Date:
2007-5-2
ApplicationType:
Invention
State/Country:
11[China|beijing]
IPC:
H03K 19/094
Applicant(s):
Tsinghua University
Inventor(s):
Yang Huazhong, Wang Yu, Luo Rong
Key Words:
reducing method, circuit power consumption, large scale integrated circuit
Abstract:
The invention relates to a method for reducing power loss in large-scale IC, firstly setting the threshold value of each logic door in the circuit as a low threshold value, calculating delay time and maximum buffering time of a logic door; according to the calculated result, reallocating the buffering time of each logic door in the circuit to make the buffering time of each logic door greater than its difference between delay time at low threshold value and that at high threshold value; substituting the set high threshold value of logic door for the threshold value at which the buffering time of the logic door is greater than the delay time difference. On the premise of assuring circuit functions, it reduces the number of low-threshold value logic doors by a large margin and then reduces the power loss caused by current leakage in the circuit.
Claim:
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