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A method for reducing power lead current in integrated circuit
Title：	A method for reducing power lead current in integrated circuit
Application Number：	200410037661	Application Date：	2004/04/29
Announcement Date：	2005/01/26	Pub. Date：
Publication Number：	1571139	Announcement Number：
Grant Date：		Granted Pub. Date：
ApplicationType：	Invention	State/Country：	11[China|beijing]
IPC：	G06F 17/50, H01L 21/82, H01L 27/00
Applicant(s)：	Tsinghua University
Inventor(s)：	Yang Huazhong, Wang Yu, Luo Rong
Key Words：	reducing method, power lead current, integrated circuit
Abstract：	The invention relates to a method for reducing power line current in IC, firstly dividing synchronous time sequence circuit into many parallel circuits; making static time sequence analysis on these parallel circuits to obtain the time sequence of each of them; according to the time sequence of each parallel circuit, adding a different delay time to original clock of the parallel circuit to make the clock phases of all the parallel circuits different; using original clock to compensate the phase of output signal of each parallel to synchronize all the output signals. The method uses a corresponding clock to each parallel circuit whose turning time is staggered, thus making the current in each circuit reach the peak value at a different time, reducing peak current of the total circuit and its change trend, and thus reducing ohm voltage drop of power supply/ground wire net and the partial noise that the digital circuit injects into the substrate.
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