Design method of 0.35 um LDMOS high vltage power displaying driving element
Title：
Design method of 0.35 um LDMOS high vltage power displaying driving element
Application Number：
 200410003469
Application Date：
 2004/03/26
Announcement Date：
 2005/01/12
Pub. Date：
Publication Number：
 1564318
Announcement Number：
Grant Date：
Granted Pub. Date：
ApplicationType：
 Invention
State/Country：
 11[China|beijing]
IPC：
 G09G 3/00, H01L 21/70, H01L 51/00
Applicant(s)：
 Tsinghua Univ.
Inventor(s)：
 Wang Jimin, Cao Lin, Xiao Wenrui
Key Words：
 Design method, 0.35 um, LDMOS, high vltage, power displaying, driving element
Abstract：
 Base on compatible standard 0.5 micro technique, two times of ion implantation in P, N channel regions, and two times of ion implantation in P, N drift regions are added in the invention. The procedures adopted in the invention are as following: reaching thickness in 100 Angstrom of gate oxidizing layer; injecting boron and phosphorus impurities after forming polysilicon gate; forming channels in 0.3-0.4 micro, short drift region and P, N MOS devices through transverse diffusion and self alignment. On P trap, one time of ion implantation in drift region and one time of doping injection in channel region produces PMOS device. One time of ion implantation in P drift region on N trap and one time of doping injection in channel region produces NMOS device. Features are small area of tube core, and large driving current.
Claim：
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PCT：
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