Abstract： |
The invention is in the field of phase-locked ring integer circuit. It is characterized in that it is formed by four cascade difference interlocks; the input ends of one group of difference clock signal are separately connected with the I end, Q end and I and Q end of the second mater-slave flip-flop of the frequency divider which is formed by the two cascade flip-flops; the input ends of the other group of difference clock signal are separately connected with the I end, Q end and I and Q end; the output phase of I end, Q end and I and Q end are in turn different with 0 deg., 90 deg., 180 deg., and 270 deg. clock signal so that the input clock of each interlock is different with 180 deg.; the data output end D and D end of second, third and fourth grade interlock are connected with the front grade interlock Q and Q end; the D and D end of the first interlock are connected with fourth interlock Q and Q end; each interlock outputs two clock phase fixed data signals p0 and p4, p1 and p5, p2 and p6, p3 and p7 on the Q and Q end, wherein each pair of data signal is different with 180 deg. |
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