Precharge CMOS trigger with low-leakage low clock signal oscillation condition
Title：
Precharge CMOS trigger with low-leakage low clock signal oscillation condition
Application Number：
 200510086916
Application Date：
 2005/11/18
Announcement Date：
 2006/04/12
Pub. Date：
Publication Number：
 1758537
Announcement Number：
Grant Date：
Granted Pub. Date：
ApplicationType：
 Invention
State/Country：
 11[China|beijing]
IPC：
 H03K 3/012, H03K 3/356, H03K 3/00
Applicant(s)：
 Tsinghua Univ.
Inventor(s)：
 Yang Huazhong, Qiao Fei, Wang Xun
Key Words：
 low-leakage, low clock signal oscillation, condition precharge, CMOS trigger
Abstract：
 This invention relates to the CMOS trigger technology characterizing that the first level flip-latch is applied with a modified condition pre-charge control circuit controlled by input data to reduce the dynamic power loss of the trigger and leaked current power loss, two output nodes of the first level flip-latch are connected to two independent single clock flip-latches with the same circuit parameter to guarantee the symmetric rising and falling time delay of the compensated output end of the trigger, the clock signal is connected onto a NMOS tube controlling the charge circuit to reduce the parasitic condenser of the charge path and increase the velocity of the circuit and reduce the structure by reducing extra high voltage supply line providing offset substrate.
Claim：
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2008-4-17
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