Quasi-circulation low density parity code encoder and check bit generating method |
Title： |
| Quasi-circulation low density parity code encoder and check bit generating method |
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Application Number： |
200710176161 |
Application Date： |
2007/10/22 |
Announcement Date： |
2008/03/12 |
Pub. Date： |
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Publication Number： |
101141132 |
Announcement Number： |
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Grant Date： |
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Granted Pub. Date： |
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ApplicationType： |
Invention |
State/Country： |
11[China|beijing] |
IPC： |
H03M 13/11 |
Applicant(s)： |
Tsinghua University |
Inventor(s)： |
Yang Zhihang, Xie Qiuliang, Peng Kewu, Wang Jintao, Song Jian |
Key Words： |
Quasi-circulation, low density, parity code, encoder, check bit, generating method |
Abstract： |
The invention discloses a quasi-cycle low density parity checking code encoder and the parity bit generating method and consists of a serial/parallel switch unit, an encoding matrix storage unit, an information bit cache unit, a core encoding unit and a serial/parallel switch unit; the method consists of: the information bit and the encoding matrix bit that is parallel input into the set width; the parallel parity bit is obtained by calculating the input parallel information and the parallel encoding matrix. The invention applies the parallel input of the information bit, the parity bit generating method of the parallel output of the parity bit into the quasi-cycle low density parity checking encoding to improve the encoding speed, save encoding source and is easy to meet half way between the encoding sources and the encoding speed. |
Claim： |
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PCT： |
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