Large number multiplier based on secondary Booth coding
Title：
Large number multiplier based on secondary Booth coding
Application Number：
 200710122086
Application Date：
 2007/09/21
Announcement Date：
 2008/02/13
Pub. Date：
Publication Number：
 101122850
Announcement Number：
Grant Date：
Granted Pub. Date：
ApplicationType：
 Invention
State/Country：
 11[China|beijing]
IPC：
 G06F 7/533
Applicant(s)：
 Tsinghua University
Inventor(s)：
 Li Shuguo, Yan Xiaodong
Key Words：
 Large number, multiplier, Booth coding
Abstract：
 A secondary Booth-code-based large number multiplier belongs to the integrated circuit design technology field of the public key encryption algorithm. The present invention uses the linear transformation formula B=8a+b to do a secondary coding to the Booth 64 algorithm results generated by the partial product. The multiplier based on the secondary Booth 64code is divided into 3-level pipelining architectures. The first level architecture precomputes the multiplicands of three times with a carry look-ahead adder and at the same time does secondary Booth coding to aj with a weight of 81 and bj with a weight of 80. The second level architecture, consisting of two identical partial products selection and compression arrays, simplifies the partial products of aj and bi respectively. The third level architecture adds the partial products of the second level by an adder. The present invention improves the multiplication rate performance and can be applied to high performance RSA and ECC chips as well as large scale PKI system of servers.
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