Low power consumption clock swing range D trigger
Title：
Low power consumption clock swing range D trigger
Application Number：
 200710119009
Application Date：
 2007/06/18
Announcement Date：
 2007/11/28
Pub. Date：
Publication Number：
 101079614
Announcement Number：
Grant Date：
Granted Pub. Date：
ApplicationType：
 Invention
State/Country：
 11[]
IPC：
 H03K 3/356H03K 3/037
Applicant(s)：
 Tsinghua University
Inventor(s)：
 Sun Yihe, Zhang Jianjun
Key Words：
 low power consumption, clock, swing range, D trigger
Abstract：
 The invention discloses a low-power consumption low-clock oscillation range D trigger in the D trigger technical domain, which is characterized by the following: the trigger adopts single power supplying for all-purpose CMOS technique; the first grade is latcher within transmitting door, clock control CMOS inverter and inverter; the output MX of the transmitting door is connected with the output of clock control CMOS inverter; the output MY of the inverter is another input of clock control CMOS inverter; the second grade is sensitive amplifier by two inverters connected from front to tail; the MX, MY are input of sensitive amplifier; the inversed output of connecting point is the output of D trigger, which affirms the correction of D trigger; the D trigger avoids individual power supplying for clock part under low clock oscillation range. The invention has low power consumption and little delay with simple structure, which reinforces the anti-noise property through difference input second grade.
Claim：
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