Automatic wiring method of analog integrated circuit based on multiple step length labyrinth algorithm
Title:
Automatic wiring method of analog integrated circuit based on multiple step length labyrinth algorithm
Application Number:
200610164921
Application Date:
2006/12/08
Announcement Date:
2007/05/16
Pub. Date:
Publication Number:
1963827
Announcement Number:
Grant Date:
Granted Pub. Date:
ApplicationType:
Invention
State/Country:
11[China|beijing]
IPC:
G06F 17/50
Applicant(s):
Tsinghua University
Inventor(s):
Hong Xianlong, Cai Yici, Du Changxu
Key Words:
multiple step length labyrinth algorithm, analog integrated circuit, automatic wiring
Abstract:
This invention belongs to VLSI physical design technique field and relates to one computer aid design method facing analogue circuit board graph, which is characterized by the following: totally according to analogue integration circuit multi-line wide binding for design to satisfy analogue circuit load current status complexity requirement. This invention comprises shortest path index method with multiple line width binding conditions and adopts starting index method to realize automatic line distribution process on network mode.
Claim:
Priority:
PCT:
LegalStatus:

Recommend this patent:
1 2 3 4 5
Average ( 0 votes):
                                                                          Recommended Patents>>

Relevancy information



Other Patents of Same Inventor

Over-all wiring method for standard units based on optimized time delay and key network techniques
Integrated circuit macro-module layout design based on module deformation and placement method
Integrated wiring method of standard units with carrying optimization of time delay based on considering coupling effect
Steiner tree method for O (nlogn) under 4-geometry
Right angle wiring tree method for wire length optimized obstacle passing
Analog circuit layout oriented symmetrical constraint extraction method based on graph isomorphism
Integrated circuit layout plan and buffer plan integrated layout method
Method for improving loading efficiency of container based on minimum freedom degree poriority principle
Rectangular steiner tree method of super large size integrated circuit avoiding barrier
Integrated circuit power supply network transient analytical solving method based on multi-layer equivalent circuit model
Large-scale hybrid mode layout method based on virtual module
Time delay driving method of right angle Steiner tree under obstruction when making loose routing for standard units
High speed high precision transient simulation method able to process tree net hybrid power supply structure in VLSI
Generally distributing method of standant unit for eliminating crosstalk caused by coupling inductance
Integrated circuit module level distributing method based on module deformation and probability local search
Crosstalk eliminating loose routing method based on power/ground grid and row alignment
Transient state analyzing method for hierarchy power supply / earth cord network based on loose operations
Standard unit overall wiring method of multi-terminal network plug-in buffer optimizing delay
Fast method for analyzing IC wiring possibility



News & Events More>>

Last Update  
2008-4-17
  Selected patents owned by Tsinghua University filed in 2005 are loaded.
2008-3-31
  Selected patents owned by Tsinghua University filed in 2006 and 2007 are load.







Copyright 2008-2015 All Rights Reserved Patent License of China.      Designed by Easygo