Analog circuit layout oriented symmetrical constraint extraction method based on graph isomorphism
Title:
Analog circuit layout oriented symmetrical constraint extraction method based on graph isomorphism
Application Number:
200410009262
Application Date:
2004/06/25
Announcement Date:
2005/03/16
Pub. Date:
2007/11/07
Publication Number:
1595403
Announcement Number:
100347708
Grant Date:
2007-11-7
Granted Pub. Date:
2007-11-7
ApplicationType:
Invention
State/Country:
11[China|beijing]
IPC:
G06F 17/50, G06F 17/30
Applicant(s):
Tsinghua University
Inventor(s):
Dong Sheqin, Hong Xianlong, Chen Song
Key Words:
Analog circuit layout, symmetrical constraint, extraction method, graph isomorphism
Abstract:
The invention relates to a symmetry constraint extraction of the analog circuit oriented mapping based on the image isomorphism, which belongs to the analog circuit automatically mapping technical field. Its characteristics lie in the following. The connection relationship between the circuit components is represented by the bisection image. Calculate a label value for each node of the image to collectively reflect the topology connection relation between the node and its perimeter ones. When the label values of two nodes are equal, they form a symmetry pair. According to the connection relation between the symmetry pair, determine the symmetry group. The invention eliminates the returning probability when forming the symmetry pair. By this means, it is highly effective and all the symmetry structures of the circuit can be found conveniently.
Claim:
Priority:
PCT:
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2008-4-17
  Selected patents owned by Tsinghua University filed in 2005 are loaded.
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