Integrated circuit layout plan and buffer plan integrated layout method |
Title: |
Integrated circuit layout plan and buffer plan integrated layout method |
|
Application Number: |
200310115545 |
Application Date: |
2003/11/28 |
Announcement Date: |
2004/11/17 |
Pub. Date: |
2006/09/13 |
Publication Number: |
1547252 |
Announcement Number: |
1275317 |
Grant Date: |
2006-9-13 |
Granted Pub. Date: |
2006-9-13 |
ApplicationType: |
Invention |
State/Country: |
11[China|beijing] |
IPC: |
H01L 21/82G06F 17/50 |
Applicant(s): |
Tsinghua University |
Inventor(s): |
Hong Xianlong, Dong Sheqin, Cai Yici |
Key Words: |
Integrated circuit, layout plan, buffer, layout method |
Abstract: |
The invention is a distribution method integrating the integrated circuit distribution plan and the buffer plan, the invention belongs to computer aided design for integrated circuit field. The character lies in: it introduces the feasible area calculation when the buffer is inserted in, and simplifies the complexity of the buffer distribution through distribution of the blank area in the plan result, the design is carried on pointing to the solution procedure to the simulated quenching by the buffer distribution, the distribution of the buffer is integrated in the solution of the distribution plan. The buffer distribution is leaded in the optimization process of the wiring plan, realizes the optimization to the delay performance. |
Claim: |
|
Priority: |
|
PCT: |
|
LegalStatus: |
|