Split network processor control information cache memory
Title:
Split network processor control information cache memory
Application Number:
200610011425
Application Date:
2006/03/03
Announcement Date:
2006/08/02
Pub. Date:
Publication Number:
1812379
Announcement Number:
Grant Date:
Granted Pub. Date:
ApplicationType:
Invention
State/Country:
11[China|beijing]
IPC:
H04L 12/56
Applicant(s):
Tsinghua Univ.
Inventor(s):
Liu Zhen, Liu Bin
Key Words:
Split network processor control information, cache memory
Abstract:
This invention relates to split network processor controlling information high-speed buffer memory. It concludes: address identifier, which specifies the application correlated data or flow correlated data App-Cache, which buffer stores application correlated data Flow-Cache, which buffer stores flow correlated data memory dispatcher, which dispatches the controlling information memory access requests coming from App-Cache and Flow-Cache. Flow-Cache is arranged with two work stacks so that when the processing element is using flow correlated data of one work stack to process data packet, the other work stack can read-in related flow correlated data to the next data packet by use of controlling information expected address coming from flow classifier. If the flow correlated controlling information is modified by processing element, when replacement takes place, the modified part should be written back to controlling information memory.
Claim:
Priority:
PCT:
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