Flow receiving taking and statistic circuit assembly for 10G network performance tester |
Title： |
| Flow receiving taking and statistic circuit assembly for 10G network performance tester |
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Application Number： |
200510011711 |
Application Date： |
2005/05/13 |
Announcement Date： |
2005/10/26 |
Pub. Date： |
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Publication Number： |
1688135 |
Announcement Number： |
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Grant Date： |
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Granted Pub. Date： |
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ApplicationType： |
Invention |
State/Country： |
11[China|beijing] |
IPC： |
H04L 12/26, H04L 12/56 |
Applicant(s)： |
Tsinghua Univ. |
Inventor(s)： |
Chen Rongdi, Wu Jianping, Zhang Tielei, Zhang Xiaoping |
Key Words： |
10G network, performance tester, flow receiving taking, statistic circuit, assembly |
Abstract： |
This invention relates to a flow receiving, gripping and calculating circuit component for a 10G network performance test instrument characterizing in separating the data into two parts with a branch circuit after receiving the frame data from a frame controller by the PL4 IP core receiver, one part passing through the protocol sending circuit and a related storage is fetched by CPU via the CPU interface circuit to be sent to an upper level applied program, the other part passes through the data analysis pre-process circuit to carry out the flow and ping packet statistics to be sent to CPU via related interface circuit and to the data packet gripping circuit, which decides datum that should be written into the outboard SRAM based on the plan and generates a written, request signal to be sent to the arbitration circuit to arbitrate and select from the read-write instructions. |
Claim： |
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Priority： |
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PCT： |
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LegalStatus： |
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