Standard unit overall wiring method of multi-terminal network plug-in buffer optimizing delay
Title:
Standard unit overall wiring method of multi-terminal network plug-in buffer optimizing delay
Application Number:
200510011712
Application Date:
2005/05/13
Announcement Date:
2005/10/26
Pub. Date:
2007/11/07
Publication Number:
1687934
Announcement Number:
100347710
Grant Date:
2007-11-7
Granted Pub. Date:
2007-11-7
ApplicationType:
Invention
State/Country:
11[China|beijing]
IPC:
G06F 17/50
Applicant(s):
Tsinghua Univ.
Inventor(s):
Hong Xianlong, Jing Tong, Xu Jingyu
Key Words:
multi-terminal network, plug-in buffer, optimizing delay, standard unit, overall wiring
Abstract:
The invention is a standard cell general wiring method for optimizing time delay by inserting buffers in multi-end line network, belonging to IC CAD technical field, and characterized in: as optimizing circuit time delay, firstly using the known standard cell general wiring method that optimizes the time delay based on key network technique to construct a key network for the circuit, and then using the minimum cutting method to find a group of line networks obviously optimizing time delay but little worsening the jam; after replacing a multi-end line network among them with a time delay optimum wiring tree, in the paths from source node to key drain points, firstly converting the time delay optimum wiring tree to a branched wiring tree, then according to the SAKURAI time delay calculating formula, selecting a node with the maximum improved value from the optimum insert point and branched insert point in the path during time delay improving; then judging if the node accords to initial restriction index. Relative to the traditional methods, the invention can obtain the outstanding time delay optimized result within a shorter time.
Claim:
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PCT:
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